Delay estimation in IC design is desirable, as logic cells typically require the convergence of multiple signals within a certain time window for the logic flow to proceed without error. Monte Carlo (MC) simulations are often used to estimate design yields for manufacturing processes governed by random variables. Given the size and complexity of current IC designs, MC simulations are computationally expensive. Accordingly, a full statistical distribution in terms of process parameters (e.g., signal delay) is desirably obtained by supplementing a limited number of MC simulations with additional techniques (e.g., static timing analysis, STA, and the like). However, current STA analysis typically fail to accurately predict statistical distributions that have large skewness (e.g., highly non-Gaussian). Thus, in many instances, in-lieu of an accurate STA analysis, current techniques use overly pessimistic approaches, resulting in inefficient IC designs.
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